Department Manager, HITACHI
Masanao Yamaoka received the B.E., M.E., and Ph. D degrees in electronics and communication engineering from Kyoto University, Kyoto, Japan, in 1996, 1998, and 2007, respectively. In 1998, he joined the Central Research Laboratory, Hitachi, Ltd., Tokyo, Japan, where he was engaged in the research and development on low-power embedded SRAM and CMOS circuits. Since 2012, he has been engaged in the research of new-paradigm computing using CMOS circuits. Now he leads the CMOS annealing R&D team.