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Designing Low Power Edge ML Hardware Using High-Level Synthesis

January 15, 202014:00 - 14:30State of AI and ML - January 2020


Ellie Burns

Ellie Burns

Director of Marketing, Mentor, A Siemens Business
  • January 15, 2020
  • 02:00pm - 02:30pm


Many companies will soon start, or have already started, adding machine learning inferencing hardware to their mobile devices. As a tools provider, we have been able to observe what approaches have worked well and where teams struggle during their design process.

Lowering power consumption for machine learning (ML) inferencing hardware is required to move more ML applications from the cloud to edge devices. We have observed that RTL design teams struggle to complete ML inferencing hardware on schedule. Time pressure leads hardware teams to select sub-optimal architectures, use overbuilt off-the-shelf solutions, or to abandon projects. Traditional RTL design and verification cannot keep up with the rapid changes and growing complexity of machine learning algorithms.

In order to improve design and verification productivity by 25-50%, ML hardware designers should model and test hardware at a higher level of abstraction using C++/SystemC. High-Level Synthesis (HLS) then optimizes and generates RTL for ASIC or FPGA. Design teams are able to develop novel architectures in C++/SystemC and then use HLS to quickly synthesize RTL, tuning for power, area, performance, and memory architecture using synthesis constraints.

HLS has been used for over ten years by companies like NVidia, Google and Qualcomm. Come and see how ML inferencing hardware teams lower stress and build better hardware using HLS.